The present invention generally relates to memory architecture, in particular to a memory circuit.
With every new generation of processors, the number and density of its memory cells typically increases. As a consequence, the probability of defective memory cells and/or connections between the memory cells usually augments as well.
To ameliorate the effect of defects, spare cells are often incorporated into a memory and substituted for defective cells as needed during a test procedure following the manufacturing process. While this technique may increase the yield, the potential current load of the additional circuitry to effect a substitution of good cells for defective cells, and the potential current load imposed by defective cells remaining in the memory after being functionally replaced may be detrimental. An increased load on ancillary driver circuits can slow the operation of the circuits, increasing access time. Also energy consumption may increase, resulting in higher energy and cooling costs, higher temperatures, and decreased reliability.